• DocumentCode
    2283501
  • Title

    Temperature-sensitive loop parallelization for chip multiprocessors

  • Author

    Narayanan, Sri Hari Krishna ; Chen, Guilin ; Kandemir, Mahmut ; Xie, Yuan

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., USA
  • fYear
    2005
  • fDate
    2-5 Oct. 2005
  • Firstpage
    677
  • Lastpage
    682
  • Abstract
    In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to reduce the peak temperature. Our experimental results show that the peak (average) temperature can be reduced by 20.9°C (4.3°C) when averaged over all the applications tested, incurring small performance/power penalties.
  • Keywords
    microprocessor chips; parallelising compilers; thermal management (packaging); 20.9 C; 4.3 C; chip multiprocessors; peak temperature; temperature-sensitive loop parallelization; Application software; Energy consumption; Hardware; Power dissipation; Processor scheduling; Runtime; Software performance; Software testing; System testing; Temperature;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on
  • Print_ISBN
    0-7695-2451-6
  • Type

    conf

  • DOI
    10.1109/ICCD.2005.105
  • Filename
    1524225
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2283501