Title :
High-performance CMOS fabricated on ultrathin BESOI with sub-10 nm ttv
Author :
Iyer, Srikanth S. ; Tejwani, M.J. ; Pitner, P.M. ; Sedgwick, T.O. ; Shahidi, G.G.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Ultra thin Bond and Etch-back Silicon On Insulator (BESOI) in the thickness range of 75 to 100 nn offers the potential for performance enhancement in both CMOS and BiCMOS technology. To be useful, however, a very low total thickness variation (ttv) is desirable, typically below 10 nm. SIMOX can obtain high uniformity, but has high residual defect densities. Recently, a plasma-based thinning process has been able to demonstrate impressive results in thinning conventional bonded SOI wafers to ultra thin high ttv dimensions
Keywords :
BiCMOS integrated circuits; CMOS integrated circuits; integrated circuit technology; semiconductor-insulator boundaries; silicon; sputter etching; wafer bonding; 75 to 100 nm; BiCMOS technology; IC fabrication; Si; bonded SOI wafers; high-performance CMOS; plasma-based thinning process; total thickness variation; ultrathin bond/etch-back SOI; CMOS process; CMOS technology; Conferences; Electron devices; MOS devices; Ring oscillators; Voltage; Wafer bonding;
Conference_Titel :
SOI Conference, 1993. Proceedings., 1993 IEEE International
Conference_Location :
Palm Springs, CA
Print_ISBN :
0-7803-1346-1
DOI :
10.1109/SOI.1993.344562
