Performance issues of SOI CMOS circuits at low supply voltages

Circuit applications working at typical battery voltages (1.35…1.55 V) promise to be an interesting market for SOI technology. Reduced extrinsic capacitances, low leakage currents, nearly ideal subthreshold slopes and improved scalability offer several advantages over conventional CMOS circuits, particularly in regard of power consumption and circuit speed In this paper we use the SPICE implementation of our charge sheet model of the thin-film SOI MOSFET to investigate quantitatively the performance of digital SOI CMOS circuits in the voltage range from 1 to 2 V. The charge sheet principle allows us to include the subthreshold range into the simulation without losing the consistency with well established strong inversion models. The calculations are based on a SIMOX process with t_of=20 nm, t _b=80 nm, t_ob=350 nm. The threshold voltages of the n-channel and p-channel transistors are assumed to be 0.4 V and 0.5 V, respectively. Most of the model parameters for both SOI and bulk silicon MOS devices-the latter ones are described with the SPICE Level 3 MOSFET model-have been extracted from numerical device simulations