Title :
Selection of operation mode on SOI/MOSFETs for high-resistivity load static memory cell
Author :
Inoue, Y. ; Yamaguchi, Y. ; Yamaguchi, T. ; Takahashi, J. ; Iwamatsu, T. ; Wada, T. ; Nishimura, Y. ; Nishimura, T. ; Tsubouchi, N.
Author_Institution :
LSI Res. & Dev. Lab., Mitsubishi Electr. Corp., Itami, Japan
Abstract :
SOI/MOSFETs are widely known to have some advantages such as reduction of parasitic capacitance, improvement of subthreshold characteristics and increased drive current, compared with bulk-Si/MOSFETs. Moreover, this structure provides the reduction in the substrate-bias effect because the back-gate bias (Si substrate) is applied to the channel region through thick buried oxide. In the present paper, we propose the best choice of operation mode of SOI/MOSFETs in a high-resistivity load SRAM cell to improve the stability in the memory cell and to obtain sufficient static noise margin providing non-destructive reading of cell data at low supply voltage
Keywords :
MOS integrated circuits; SRAM chips; insulated gate field effect transistors; nondestructive readout; semiconductor device noise; semiconductor-insulator boundaries; silicon; stability; SOI MOSFETs; SRAM cell; Si; back-gate bias; channel region; drive current; high-resistivity load; low supply voltage; nondestructive reading; operation mode selection; parasitic capacitance reduction; stability; static memory cell; static noise margin; substrate-bias effect; subthreshold characteristics; thick buried oxide; Circuit noise; Circuit simulation; Circuit stability; Inverters; Large scale integration; MOSFETs; Random access memory; Silicon on insulator technology; Substrates; Threshold voltage;
Conference_Titel :
SOI Conference, 1993. Proceedings., 1993 IEEE International
Conference_Location :
Palm Springs, CA
Print_ISBN :
0-7803-1346-1
DOI :
10.1109/SOI.1993.344575
