FPGA implementation of Addition/Subtraction module for double precision floating point numbers using Verilog

The floating point operations are critical to implement on FPGAs due to their complexity of their algorithms. Thus, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, in this paper the proposed work is explored FPGA implementation of Addition/Subtraction for IEEE double precision floating point numbers. This kind of unit can be extremely useful in the FPGA implementation of complex systems that benefits from the parallelism of the FPGA device. The design is in Verilog Hardware description language (HDL) and implemented on FPGA. The verilog code first simulated with isim and synthesized on Xilinx ISE14.1i.