Design and Integration of Parallel Hough-Transform Chips for High-speed Line Detection

Author

Chern, Ming-Yang ; Lu, Yi-Hsiang

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Cheng Univ.

Volume

2

fYear

2005

fDate

22-22 July 2005

Firstpage

42

Lastpage

46

Abstract

Line detection is often needed in computer vision applications. The Hough transform processing of image data for line detection is robust but time-consuming. With the use of multiple processors, the processing time for Hough transform can be much reduced. In our research, we design an array processor for line-detection based on Hough transform that performs the line-parameter calculation and accumulation for different angles in parallel. Such an array processor together with its parallel peak extraction circuits have been implemented on a single chip. Based on the TSMC 0.35mum CMOS technology, the fabricated chip (with 10 processors) can be run successfully up to the clock rate of 50MHz. This paper presents the SOC design that can be extended to the integration of multiple chips to form a faster system with more parallel processors

Keywords

CMOS integrated circuits; Hough transforms; computer vision; integrated circuit design; parallel processing; system-on-chip; Hough transform processing; SOC design; TSMC CMOS technology; array processor design; computer vision; high-speed line detection; parallel Hough-transform chip design; parallel peak extraction circuit; parallel processor; Application software; CMOS process; CMOS technology; Circuits; Clocks; Computer vision; Embedded system; Image edge detection; Process design; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Systems, 2005. Proceedings. 11th International Conference on

Conference_Location

Fukuoka

ISSN

1521-9097

Print_ISBN

0-7695-2281-5

Type

conf

DOI

10.1109/ICPADS.2005.126

Filename

1524247