Improved power supply rejection (PSR) digital comparator based Flash analog to digital converter (FADC)

In this paper Flash ADC is designed using improved PSR digital comparator approach for effective speed and power improvement by eliminating complete resistive ladder circuit. Comparator used in this design is with improved power supply rejection ratio compared to TIQ (threshold inverter quantization) comparators. Additional clocking strategy is incorporated which leads to elimination of sample and hold circuit. Thermometer to binary decoder with low power consumption, less area & short critical path is selected for the design of low power high speed FADC. Presence of bubble error reduces output correction capability. An advanced bubble error correction scheme is proposed associated with Multiplexer based decoder.