A 40 Mbit/s soft output Viterbi decoding ASIC

Decoding algorithms that make not only use of soft quantized inputs but also deliver soft decision outputs have attracted considerable interest. This was motivated by newly developed soft output algorithms with reduced complexity and advances in VLSI technology. The authors present, to the best of their knowledge, the first high speed VLSI implementation of the soft output Viterbi algorithm. The 43 mm² chip is designed for a 16 state convolutional code, and tested samples achieved a throughput of 50 Mbit/s. It is thus demonstrated that transmission schemes using soft output decoding can be considered practical even at very high throughputs. Since such decoding systems are more complex to design than hard output systems special emphasis is placed on the employed design methodology