DocumentCode :
2284495
Title :
A 40 Mbit/s soft output Viterbi decoding ASIC
Author :
Joeressen, Olaf J. ; Meyr, Heinrich
Author_Institution :
Integrated Syst. for Signal Process., Tech. Hochschule Aachen, Germany
Volume :
3
fYear :
1994
fDate :
28 Nov- 2 Dec 1994
Firstpage :
1482
Abstract :
Decoding algorithms that make not only use of soft quantized inputs but also deliver soft decision outputs have attracted considerable interest. This was motivated by newly developed soft output algorithms with reduced complexity and advances in VLSI technology. The authors present, to the best of their knowledge, the first high speed VLSI implementation of the soft output Viterbi algorithm. The 43 mm2 chip is designed for a 16 state convolutional code, and tested samples achieved a throughput of 50 Mbit/s. It is thus demonstrated that transmission schemes using soft output decoding can be considered practical even at very high throughputs. Since such decoding systems are more complex to design than hard output systems special emphasis is placed on the employed design methodology
Keywords :
VLSI; Viterbi decoding; application specific integrated circuits; channel capacity; computational complexity; convolutional codes; digital signal processing chips; 16 state convolutional code; 40 Mbit/s; 40 Mbit/s soft output Viterbi decoding ASIC; VLSI; complexity; decoding algorithms; design methodology; soft decision outputs; soft quantized inputs; throughput; transmission schemes; Algorithm design and analysis; Application specific integrated circuits; Channel coding; Convolutional codes; Decoding; Signal processing algorithms; Testing; Throughput; Very large scale integration; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Global Telecommunications Conference, 1994. GLOBECOM '94. Communications: The Global Bridge., IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-1820-X
Type :
conf
DOI :
10.1109/GLOCOM.1994.513023
Filename :
513023
Link To Document :
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