Power and performance efficient secondary cache using tag bloom architecture

Among cache write-through and write-back policies, write-through policy is more efficient and offers better performance in high performance microprocessors. In write-through policy, write is done synchronously both to cache and main memory. But, write-through policy causes large energy overhead due to frequent lower lever cache accesses during write operations. A new cache architecture called Tag-Bloom cache is proposed in order to reduce the power consumption. Here, a tag is attached to each way in the L2 cache. This way tag is stored in way-tag array in L1 cache. Utilizing these tags, L2 cache can be accessed as a direct mapping cache during subsequent write hits, thereby power consumption is reduced. A Bloom Filter is introduced to accurately predict the cache miss and hot/cold checks. A considerable energy saving is obtained based on SPEC CPU2000 benchmarks along with a small area overhead and no performance degradation. High-performance microprocessors now-a-days use longer addresses and hence cache tag arrays become longer. This concept of Tag-Bloom can be applied to other existing cache design techniques to achieve further power reduction.