A new hybrid multiplieusing Dadda and Wallace method

In recent trend, power management has become critical concern due to portable applications. High power dissipation increases temperature profile of the chip and affects the performance of the design. Many techniques at different levels of design process have been recommended to reduce the power dissipation. Multiplier is one of the major sources of power dissipation in application systems like Digital Signal Processor (DSP), Microprocessor and Application Specific Integrated Circuits (ASIC´S). High speed multiplication is a primary requirement of high performance computing systems. Designing multiplier with low power, high processing speed and minimal layout structure are of prime importance. In this paper, we propose 8*8 hybrid tree multiplier by combining both Wallace and Dadda methods. The design is implemented and simulated by DSCH2 and MICROWIND tool. The result shows that 40 % of power reduction can be achieved.