A 3.4 ns 0.8 /spl mu/m BiCMOS 53/spl times/53 b multiplier tree

Author

Hilker, S. ; Phan, N. ; Rainey, D.

Author_Institution

IBM Corp., Rochester, MN, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

292

Lastpage

293

Abstract

A 53/spl times/53 b multiplier tree with 3.4 ns latency, 10 mm/sup 2/ active area, and 5 W power dissipation at 200 MHz and 3.6 V supply is implemented in 0.8 /spl mu/m n-well BiCMOS with 115 /spl Aring/ gate oxide, 0.45 /spl mu/m effective channel length, and 4 levels of metal. This 3.4ns low-latency multiplier is for a floating-point unit (FPU) on a BiCMOS RISC processor capable of performing IEEE double precision multiply-add operations in three pipelined stages at 200MHz (15ns latency, 5ns throughput, 400MFLOPs peak rate) using multiply-add fused dataflow.<>

Keywords

BiCMOS integrated circuits; digital arithmetic; multiplying circuits; parallel processing; pipeline processing; reduced instruction set computing; 0.8 micron; 200 MHz; 3.4 ns; 3.6 V; 400 MFLOPS; 5 W; IEEE double precision multiply-add operations; RISC processor; effective channel length; floating-point unit; latency; multiplier tree; multiply-add fused dataflow; n-well BiCMOS; pipelined stages; power dissipation; Adders; BiCMOS integrated circuits; Circuit noise; Circuit testing; Clocks; Delay; Logic circuits; Low-frequency noise; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344636

Filename

344636