A 4.5 mm/sup 2/ multiplier array for a 200 MFLOP pipelined coprocessor

Author

Heikes, C.

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

290

Lastpage

291

Abstract

This multiplier array is used in the floating point coprocessor that is part of several PA-RISC processor chips. This coprocessor is single- and double-precision IEEE compliant and is implemented in a 3-level-metal 0.8 /spl mu/m CMOS process. The floating point unit is comprised of a pipelined ALU, a pipelined multiplier, a divide and square-root unit, a 32/spl times/64 b register file and a control unit. Each of these units operates independently, allowing concurrent operations. The latency is nominally 20 ns for addition, multiplication and data conversions with a new issue every 10 ns. The latency of a single-precision divide or square-root is 80 ns.<>

Keywords

CMOS integrated circuits; digital arithmetic; integrated logic circuits; logic arrays; microprocessor chips; multiplying circuits; pipeline processing; reduced instruction set computing; 0.8 micron; 20 ns; 200 MFLOPS; 4.5 mm; CMOS process; PA-RISC processor chips; concurrent operations; divide and square-root unit; double-precision IEEE compliant; floating point coprocessor; latency; multiplier array; pipelined ALU; pipelined coprocessor; pipelined multiplier; single-precision IEEE compliant; three-level-metal process; Adders; Clocks; Coprocessors; Delay; Latches; Logic arrays; Multiplexing; Phased arrays; Pipelines; Uncertainty;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344637

Filename

344637