Modified selective way based trace cache

Performance efficient instruction fetch unit is a critical issue in superscalar processor design (Smith and Sohi, 1995). Trace cache which stores traces of the dynamic instruction stream is a major part of such fetch units. Conventional trace cache was implemented as a set associative structure where it is needed to probe all the ways in the particular set in order to look for the required entry (Rotenberg, et.al., 1996). Selective way based trace cache (SWTC) was a modified trace cache where only the selected way(s) are probed instead of probing all the ways (Zeng, et.al., 2009). Here, traces are divided into several types and stored into cache by type. In this paper, the mapping policy of the SWTC is used to propose a modified design. Simulation results show that the proposed design performs better than the earlier SWTC model. On comparing with the trace cache(TC), the proposed design shows a 4.68% improvement in performance in terms of instructions committed per cycle (IPC).