An analog front-end signal processor for a 64 Mb/s PRML hard-disk drive channel

Author

Choi, D. ; Pierson, R. ; Trafton, F. ; Sheahan, B. ; Gopinathan, V. ; Mayfield, G. ; Ranmuthu, I. ; Venkatraman, S. ; Pawar, V. ; Lee, O. ; Giolma, W. ; Krenik, W. ; Abbott, W. ; Johnson, K.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

282

Lastpage

283

Abstract

Synchronous channel designs, such as partial response maximum likelihood (PRML), are viable for high areal density on a hard-disk drive (HDD). Previously-published PRML channels include a 56 Mb/s channel design but without an on-chip programmable filter, synthesizer or servo demodulator. This 5V BiCMOS integrated circuit contains all the analog front-end functions necessary for a 64Mb/s HDD channel using a rate-8/9 code.<>

Keywords

BiCMOS integrated circuits; analogue processing circuits; hard discs; linear integrated circuits; maximum likelihood estimation; signal detection; 5 V; 64 Mbit/s; BiCMOS; PRML; analog front-end functions; analog front-end signal processor; areal density; hard-disk drive channel; partial response maximum likelihood; rate-8/9 code; synchronous channel designs; Digital filters; Digital magnetic recording; Hard disks; Jitter; Magnetic recording; Magnetic separation; Phase locked loops; Signal processing; Switches; Temperature control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344640

Filename

344640