Title :
A 100 MHz output rate analog-to-digital interface for PRML magnetic-disk read channels in 1.2 /spl mu/m CMOS
Author :
Uehara, G.T. ; Gray, P.R.
Author_Institution :
California Univ., Berkeley, CA, USA
Abstract :
A key element in the signal path of magnetic-disk read channels employing digital implementations of PRML and other discrete-time signalling approaches is the analog-to-digital (A/D) interface containing a pre-filter, sampler, and analog-to-digital converter (ADC). The pre-filter performs noise filtering, anti-aliasing, and pre-equalization prior to sampling and conversion to the digital domain. At symbol rates of 100 MHz and above, envisioned in the future, implementation of the required filtering is difficult using conventional approaches. This paper describes a filter/ADC combination that uses a switched-capacitor FIR passive sampling approach.<>
Keywords :
CMOS integrated circuits; analogue-digital conversion; magnetic disc storage; maximum likelihood estimation; signal detection; switched capacitor filters; 1.2 micron; 100 MHz; CMOS; PRML magnetic-disk read channels; analog-to-digital converter; analog-to-digital interface; anti-aliasing; discrete-time signalling; noise filtering; partial response maximum likelihood; pre-equalization; pre-filter; sampler; switched-capacitor FIR passive sampling; Band pass filters; Bandwidth; Capacitors; Clocks; Filtering; Finite impulse response filter; Prototypes; Sampling methods; Switches; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344641
