Title :
1.2 V mixed analog/digital circuits using 0.3 /spl mu/m CMOS LSI technology
Author :
Matsuura, T. ; Yano, K. ; Hiraki, M. ; Sasaki, Y. ; Miyamoto, M. ; Ishii, T. ; Nagai, R. ; Nishida, T. ; Seki, K. ; Imaizumi, E. ; Anbo, T. ; Sumi, N. ; Rikino, K.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
Abstract :
Although dropping the supply voltage below 2 V is effective in reducing power consumption of LSIs for low-power systems, it has not been adopted because it severely degrades the system performance. This paper reports an experimental 1.2 V mixed analog/digital LSI based on 0.3 /spl mu/m laterally-doped buried-layer (LDB) CMOS with /spl plusmn/0.4 V threshold voltages. Based on circuits such as a double feedforward phase-compensated amplifier and a self current cut-off sense amplifier, a 9b 2 MHz 4 mW pipelined A/D converter, a 16 kb 2 mW SRAM with 32 ns access time, and a basic logic gate with a 400 ps delay and 0.4 /spl mu/W/MHz dissipation are realized.<>
Keywords :
CMOS integrated circuits; SRAM chips; amplifiers; analogue-digital conversion; integrated logic circuits; large scale integration; linear integrated circuits; logic gates; mixed analogue-digital integrated circuits; 0.3 micron; 1.2 V; 16 kbit; 2 MHz; 2 mW; 32 ns; 4 mW; 400 ps; 9 bit; ADC; CMOS LSI technology; SRAM; double feedforward phase-compensated amplifier; laterally-doped buried-layer CMOS; logic gate; low-power systems; mixed analog/digital circuits; pipelined A/D converter; self current cutoff sense amplifier; threshold voltage; CMOS analog integrated circuits; CMOS digital integrated circuits; Degradation; Digital circuits; Energy consumption; Large scale integration; Logic gates; Random access memory; System performance; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344653
