Improved fused floating point add-subtract unit for FFT implementation

This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules in terms of area, delay, power and energy. Here we have achieved reduction in area (in terms of LUT required) by 27.09%, reduced delay by 17.10%, reduction in power consumption by 11 % and energy is reduced by 26.22% as compared to discrete implementation.