Title :
A 500 MHz 32b 0.4 /spl mu/m CMOS RISC processor LSI
Author :
Suzuki, K. ; Yamashina, M. ; Nakayama, T. ; Izumikawa, M. ; Nomura, M. ; Igura, H. ; Heiuchi, H. ; Goto, J. ; Inoue, T. ; Koseki, Y. ; Abiko, H. ; Okabe, K. ; Ono, A. ; Yano, Y. ; Yamada, H.
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
This 500 MHz, 32b, reduced-instruction-set-computer (RISC) microprocessor uses 0.4 /spl mu/m CMOS technology. The microprocessor has an 8-stage pipelined data path. The 8 pipeline stages are: (1) instruction fetch 1 (I1); (2) instruction fetch 2 (I2); (3) register file fetch and instruction decode (RF); (4) execution 1 (E1); (5) execution 2 (E2); (6) data memory access 1 (D1); (7) data memory access 2 (D2); and (8) register file write-back (WB). The microprocessor includes a 32w/spl times/32b two-read/one-write register file, two double-stage pipelined 1 kB caches for both instructions and data, a 32b double-stage pipelined adder and barrel shifter, and a phase-locked loop circuit (PLL). The PLL multiplies input clock frequency by 2, 4 or 8 to obtain a 500 MHz internal clock.<>
Keywords :
CMOS integrated circuits; large scale integration; microprocessor chips; pipeline processing; reduced instruction set computing; 0.4 micron; 32 bit; 500 MHz; CMOS; LSI; RISC; barrel shifter; data memory access; input clock frequency; instruction decode; instruction fetch; microprocessor; phase-locked loop circuit; pipelined adder; pipelined data path; register file fetch; register file write-back; two-read/one-write register file; CMOS process; CMOS technology; Clocks; Decoding; Large scale integration; Microprocessors; Phase locked loops; Pipelines; Reduced instruction set computing; Registers;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344664
