Title :
Impedance of power distribution networks in TSV-based 3D-ICs
Author :
Kim, Kiyeong ; Pak, Jun So ; Kim, Heegon ; Lee, Junho ; Park, Kunwoo ; Kim, Joungho
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
Abstract :
To estimate the simultaneous switching noise (SSN) on the three dimensional VDDQ power distribution network (3D VDDQ PDN) in a TSV-based GPU system, the PDN impedance (ZPDN) and the pull up impedance (Zpull-up) of the VDDQ PDN in the GPU system were first estimated and analyzed. The GPU system consisted of a GPU, quadruple-stacked DRAMs, a silicon interposer and an organic package. The impedance estimation method, based on a segmentation method and a balanced-transmission line method (Balanced-TLM), was used for the estimation of the PDN impedance and the pull-up impedance of the 3D VDDQ PDN, combining the models of the chip PDNs, S/G lines, P/G TSV pairs, and a package PDN. The PDN impedance and the pull up impedance were also analysed with respect to the variation in the number of the P/G TSV.
Keywords :
DRAM chips; graphics processing units; integrated circuit noise; integrated circuit packaging; switching; three-dimensional integrated circuits; transmission line theory; GPU system; PDN impedance; TSV based 3D-IC; balanced transmission line method; impedance estimation method; organic package; power distribution network; pull up impedance; quadruple stacked DRAM; segmentation method; silicon interposer; switching noise; Graphics processing unit; Impedance; Inductance; Random access memory; Silicon; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2011 IEEE
Conference_Location :
Hanzhou
Print_ISBN :
978-1-4673-2288-1
Electronic_ISBN :
2151-1225
DOI :
10.1109/EDAPS.2011.6213800