A 32b 66 MHz 1.8 W microprocessor

Author

Bechade, R. ; Flaker, R. ; Kauffmann, B. ; Kenyon, S. ; London, C. ; Mahin, S. ; Nguyen, K. ; Pham, D. ; Roberts, A. ; Ventrone, S. ; VonReyn, T.

Author_Institution

IBM Corp., Essex Junction, VT, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

208

Lastpage

209

Abstract

A high-performance 32b CMOS microprocessor with an on-chip cache and low power for functional and standby modes has performance of 26MIPS and dissipates only 1.77 W in functional mode. The features include a 16 b data interface and 24 b address bus, a 16 kB four-way set associative cache, and a clock doubler for operation at 33/66 MHz. The chip is 9/spl times/7.7 mm/sup 2/. It uses single-latch LSSD design and has 99.5% stuck-at fault test coverage.<>

Keywords

CMOS integrated circuits; buffer storage; clocks; computer testing; integrated circuit testing; microprocessor chips; 1.8 W; 26 MIPS; 32 bit; 66 MHz; CMOS; address bus; clock doubler; data interface; four-way set associative cache; functional modes; high-performance microprocessor; on-chip cache; single-latch LSSD design; standby modes; stuck-at fault test coverage; Clocks; Content management; Energy management; Frequency; Microelectronics; Microprocessors; Multiplexing; Power dissipation; Power system management; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344667

Filename

344667