A 192 ks/s sigma-delta ADC with integrated decimation filters providing -97.4 dB THD

Author

Alexander, M.A. ; Mohajeri, H. ; Prayogo, J.O.

Author_Institution

Linear Div., Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

190

Lastpage

191

Abstract

Previous sigma-delta A/D converters predominantly focused on digital audio applications with sampling rates 50 kHz and below. Some modulators feature higher sampling rates, but usually lack on-chip decimation filters to complete signal processing. This monolithic sigma-delta ADC, includes a 64x oversampled 4th-order modulator, 2.5 V fully-differential bandgap reference and integrated decimation filters, with a final sampling rate of 192 kHz. The design is in a 5 V 1 /spl mu/m BiCMOS process with well-matched poly-diffusion capacitors and 6.5 GHz vertical npn bipolar transistors.<>

Keywords

BiCMOS integrated circuits; analogue-digital conversion; delta modulation; linear integrated circuits; modulators; switched capacitor networks; 1 micron; 5 V; 6.5 GHz; BiCMOS process; THD; fully-differential bandgap reference; integrated decimation filters; oversampled fourth-order SC modulator; sampling rates; sigma-delta ADC; signal processing; vertical npn bipolar transistors; well-matched poly-diffusion capacitors; BiCMOS integrated circuits; Bipolar transistors; Capacitors; Clocks; Delta-sigma modulation; Feedback; Finite impulse response filter; Operational amplifiers; Photonic band gap; Signal sampling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344675

Filename

344675