Title :
A 13.4-GHz CMOS frequency divider
Author :
Razavi, B. ; Lee, K.F. ; Ran-Hong Yan
Author_Institution :
AT&T Bell Labs., Holmdel, NJ, USA
Abstract :
This paper describes the design ofa 13.4 GHz 1/2-frequency divider fabricated in a partially-scaled 0.1 /spl mu/m bulk CMOS technology. The circuit design is heavily influenced by the device structures and layout rules. To reduce both fabrication cost and turnaround time, the CMOS process scales only channel length to 0.1 /spl mu/m and gate oxide to 40 /spl Aring/. Design rules for other dimensions correspond to a 1 /spl mu/m technology, yielding a minimum source/drain area of 2.2 /spl times/2.2 /spl mu/m/sup 2/. Thus the contribution of the source/drain junction capacitance is substantial, severely limiting speed. The divider described employs the following techniques to improve the speed: 1) nMOSFETs for sensing and regeneration and pMOSFETs for pull-up, 2) no stacked devices and pass gates, 3) ring-shaped geometry for all transistors.<>
Keywords :
CMOS integrated circuits; flip-flops; frequency dividers; integrated logic circuits; optical communication equipment; 0.1 micron; 13.4 GHz; CMOS frequency divider; bulk CMOS technology; channel length; fabrication cost; gate oxide; layout rules; minimum source/drain area; optical communication systems; ring-shaped geometry; source/drain junction capacitance; turnaround time; CMOS technology; Capacitance; Circuit simulation; Circuit synthesis; Circuit topology; Clocks; Frequency conversion; Latches; MOSFETs; Master-slave;
Conference_Titel :
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-1844-7
DOI :
10.1109/ISSCC.1994.344680
