Accurate models for CMOS scaling and gate delay in deep sub-micron regime

Author

Kai Chen ; Chenming Hu ; Peng Fang ; Gupta, A. ; Ming Ren Lin ; Wollesen, D.L.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1997

fDate

8-10 Sept. 1997

Firstpage

261

Lastpage

264

Abstract

Accurate models for drain saturation current including velocity saturation, finite thickness of inversion layer due to quantization effect, mobility degradation due to vertical electrical field in the channel, and parasitic S/D series resistance, and their experimental confirmation with measurement data are presented. Furthermore, models for load capacitance and CMOS propagation delay are proposed and experimentally confirmed.

Keywords

CMOS integrated circuits; capacitance; carrier mobility; delays; electric current; integrated circuit modelling; inversion layers; CMOS propagation delay; CMOS scaling; deep submicron regime; drain saturation current; gate delay; inversion layer thickness; load capacitance; mobility degradation; models; parasitic S/D series resistance; quantization effect; velocity saturation; vertical electrical field; Current measurement; Degradation; Delay; Electric resistance; Electric variables measurement; Electrical resistance measurement; Quantization; Semiconductor device modeling; Thickness measurement; Velocity measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on

Conference_Location

Cambridge, MA, USA

Print_ISBN

0-7803-3775-1

Type

conf

DOI

10.1109/SISPAD.1997.621387

Filename

621387