Comparative study of the proposed shifting algorithm for fault tolerance in FPGA

Today´s Field Programmable Gate Arrays (FPGAs) are being used in more exotic applications and mission critical applications. However, recent trends in current technology tend to make FPGAs less reliable. FPGA vendors have been moving down the same path of smaller device size as the rest of the semiconductor industry leading to electro migration problem and at the same time moving to larger and larger dies in order to deliver more logic gates to their customers inviting more opportunities for failure and bigger targets for gamma particles. Thus, there is a drive from the user community to improve reliability through some level of fault-tolerance. The homogeneous structure of Field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper presents a study, comparison, analysis and implementation of two available methods for swapping the configured data that is king shifting algorithm and horse shifting algorithm and further proposes a new algorithm to minimize the overall cost and improve the yield and performance parameters of system.