Title :
Power and performance fitting in nanometer design
Author :
Sato, Toshinori ; Koushiro, Takenori ; Chiyonobu, Akihiro ; Arita, Itsujiro
Author_Institution :
Dept. of Artificial Intelligence, Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Device engineers, circuit designers, and system architects are faced with many challenges. In the area of mobile and embedded computer platforms, power has already been a major design constraint. However, it is also a limiting factor in general-purpose microprocessors. In order to manage the impact of increasing microprocessor power consumption, architectural-level techniques are required as well as circuit-level design improvements. This paper proposes criticality-based instruction scheduling and Contrail processor architecture, which utilize the criticality of instructions, and demonstrates their effectiveness.
Keywords :
embedded systems; low-power electronics; microprocessor chips; mobile computing; nanoelectronics; power consumption; Contrail processor architecture; architectural-level techniques; circuit-level design improvements; criticality-based instruction scheduling; embedded computer platforms; general-purpose microprocessors; instruction criticality; microprocessor design; mobile computer platforms; nanometer design; performance fitting; power consumption; power fitting; Circuits; Design engineering; Embedded computing; Energy consumption; Energy management; Microprocessors; Mobile computing; Power engineering and energy; Power engineering computing; Power system management;
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2002. International Workshop on
Print_ISBN :
0-7695-1635-1
DOI :
10.1109/IWIA.2002.1035012