Session based core test scheduling for minimizing the testing time of 3D SOC

Author

Roy, Surajit ; Ghosh, Payel ; Rahaman, Hafizur ; Giri, Chandan

Author_Institution

Dept. of Inf. Technol., Bengal Eng. & Sci. Univ., Shibpur, India

fYear

2014

fDate

13-14 Feb. 2014

Firstpage

1

Lastpage

5

Abstract

Three dimensional (3D) VLSI integration based on through-Silicon-Via (TSV) is an emerging technology. It provides heterogeneous integration, higher performance, bandwidth, and lower power consumption. However, 3D-IC suffers from several challenges. The objective of this paper is to design the test access mechanism (TAM) architecture and test scheduling of different modules of an system-on-chip (SOC) such that the overall test time of that SOC gets reduced. In this paper we have used a session based heuristic approach to solve this problem. Experimental results have been tested on different ITC´02 benchmark SOCs that shows promising results for different TAM width allocation.

Keywords

VLSI; integrated circuit testing; scheduling; system-on-chip; three-dimensional integrated circuits; 3D SOC; ITC´02 benchmark SOCs; TAM width allocation; session based core test scheduling; session based heuristic approach; system-on-chip; test access mechanism architecture; testing time minimization; three dimensional VLSI integration; through-silicon-via technology; Abstracts; System-on-chip; Three-dimensional displays; 3D IC testing; test access mechanis; test scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics and Communication Systems (ICECS), 2014 International Conference on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-2321-2

Type

conf

DOI

10.1109/ECS.2014.6892674

Filename

6892674