19 GHz monolithic integrated clock recovery using PLL and 0.3 /spl mu/m gate-length quantum-well HEMTs

Author

Zhi-Gong Wang ; Berroth, M. ; Seibel, J. ; Hofmann, P. ; Hulsmann, A. ; Kohler, Klaus ; Raynor, B. ; Schneider, J.

Author_Institution

Fraunhofer-Inst. for Appl. Solid-State Phys., Freiburg, Germany

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

118

Lastpage

119

Abstract

ICs for optical data links have been developed for bit rates between 10 and 200 Gb/s. The only exception was the clock recovery (CR) IC at these high bit rates. In fact, the IC realization of CR is generally accepted as the weak point of high-speed system integration. While the bit rates of some ICs reach up to 40 Gb/s, monolithic ICs for a full CR function are limited to 2.5 Gb/s. The monolithic IC described here, for CR with a PLL including a full-balanced VCO, is based on the IC reported by Wang et. al. (1993). Clock frequencies up to 19 GHz are recovered with the IC reported here.<>

Keywords

clocks; field effect integrated circuits; phase-locked loops; semiconductor quantum wells; variable-frequency oscillators; 0.3 micron; 19 GHz; PLL; VCO; bit rates; clock recovery; high-speed system integration; monolithic ICs; optical data links; quantum-well HEMTs; Area measurement; Clocks; Current measurement; Electrons; Frequency; Gallium arsenide; Phase locked loops; Quantum wells; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344706

Filename

344706