• DocumentCode
    2285653
  • Title

    A 8 GHz silicon bipolar clock-recovery and data-regenerator IC

  • Author

    Pottbacker, A. ; Langmann, U.

  • Author_Institution
    Dept. of Electr. Eng., Ruhr-Univ., Bochum, Germany
  • fYear
    1994
  • fDate
    16-18 Feb. 1994
  • Firstpage
    116
  • Lastpage
    117
  • Abstract
    This contribution shows that a monolithic integrated silicon bipolar circuit can provide phase and frequency locked loop (PFLL) based clock recovery and data regeneration up to 8Gb/s. Moreover, phase and frequency detector (PFD) operation up to 15Gb/s (with an external VCO) is demonstrated. Owing to the wide tuning range of the quadrature VCO, the circuit lends itself to operation over a wide range of bit rates. Other applications of the quadrature VCO, e.g. as a synthesizer, are possible. As shown by circuit simulations, the operating frequency can be extended beyond 1OGHz, if a small unbalance between both ring oscillator stages is eliminated by minor design changes.<>
  • Keywords
    bipolar integrated circuits; clocks; data communication equipment; digital integrated circuits; phase-locked loops; signal detection; variable-frequency oscillators; 15 Gbit/s; 8 GHz; 8 Gbit/s; PFD; PFLL; Si; circuit simulations; clock recovery; data regeneration; monolithic integrated silicon bipolar circuit; phase and frequency detector; phase and frequency locked loop; quadrature VCO; ring oscillator stages; tuning; Bipolar integrated circuits; Bit rate; Circuit optimization; Clocks; Frequency locked loops; Monolithic integrated circuits; Phase detection; Phase frequency detector; Silicon; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-7803-1844-7
  • Type

    conf

  • DOI
    10.1109/ISSCC.1994.344707
  • Filename
    344707