DocumentCode :
2285684
Title :
Test scheduling with thermal optimization for network-on-chip systems using variable-rate on-chip clocking
Author :
Liu, Chunsheng ; Iyengar, Vikram
Author_Institution :
Dept. of Comput. & Electron. Eng., Nebraska-Lincoln Univ., Omaha, NE
Volume :
1
fYear :
2006
fDate :
6-10 March 2006
Abstract :
Chip overheating has become a critical problem during test of today´s complex core-based systems. In this paper, we address the overheating problem in network-on-chip (NoC) systems through thermal optimization using variable-rate on-chip clocking. We control the core temperatures during test scheduling by assigning different test clock frequencies to cores. We present two heuristics to achieve thermal optimization and reduced test time. Experimental results for example NoC systems show that the proposed method can guarantee thermal safety and yield better thermal balance, compared to previous methods using power constraints. Test application time is also reduced
Keywords :
clocks; computational complexity; embedded systems; integrated circuit testing; network-on-chip; scheduling; chip overheating; core temperatures control; network-on-chip systems; test clock frequencies; test scheduling; thermal optimization; thermal safety; variable-rate on-chip clocking; Clocks; Energy consumption; Frequency; Network-on-a-chip; Power system management; Safety; System testing; System-on-a-chip; Temperature; Thermal management;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location :
Munich
Print_ISBN :
3-9810801-1-4
Type :
conf
DOI :
10.1109/DATE.2006.244013
Filename :
1656968
Link To Document :
بازگشت