DocumentCode
2285692
Title
A monolithic 156 Mb/s clock and data-recovery PLL circuit using the sample-and-hold technique
Author
Ishihara, N. ; Akazawa, Y.
Author_Institution
NTT LSI Labs., Atsugi, Japan
fYear
1994
fDate
16-18 Feb. 1994
Firstpage
110
Lastpage
111
Abstract
The monolithic, adjustment-free clock and data-recovery PLL circuit presented in this paper has no external components except for a by-pass capacitor. A test chip fabricated using a Si bipolar process operates error-free at a 156 Mb/s rate with 2/sup 23/-1 pseudo-random bit sequence (PRBS) and data pattern jitter of 1.2/spl deg/.<>
Keywords
bipolar integrated circuits; clocks; phase-locked loops; sample and hold circuits; 156 Mbit/s; Si; Si bipolar process; adjustment-free; by-pass capacitor; chip; clock recovery; data pattern jitter; data-recovery; error-free; monolithic PLL circuit; pseudo-random bit sequence; sample-and-hold technique; Circuits; Clocks; Delay; Flip-flops; Frequency; Low pass filters; Phase locked loops; Switches; Timing; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-1844-7
Type
conf
DOI
10.1109/ISSCC.1994.344710
Filename
344710
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