• DocumentCode
    2285782
  • Title

    A networking oriented data-driven processor: CUE

  • Author

    Nishikawa, Hiroaki ; Kurebayashi, Ryosuke

  • Author_Institution
    Inst. of Inf. Sci. & Electron., Tsukuba Univ., Ibaraki, Japan
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    103
  • Lastpage
    111
  • Abstract
    This paper presents the CUE (coordinating users´ requirements and engineering constraints) processor architecture as a networking oriented processor architecture to efficiently execute media processing and protocol processing in real time. The CUE processor is a chip multiprocessor based on a dynamic data-driven scheme to exploit various levels of parallelism in problems naturally and efficiently. Since it can simultaneously execute multiple processes as long as sufficient pipeline resources are available, it can perform real-time processing without runtime overheads. Experimental results for a data-driven implementation of protocol processing in CORBA (Common Object Request Broker Architecture) demonstrate the efficiency of the real-time processing scheme. In addition, through the evaluation results of data-driven implementation of protocol and media processing, this paper re-examines heterogeneous multiprocessor configurations, instruction sets, packet formats, and the sequential processing scheme of the CUE processor.
  • Keywords
    distributed object management; multiprocessing systems; parallel architectures; protocols; real-time systems; CORBA; CUE; chip multiprocessor; dynamic data-driven scheme; engineering constraints; heterogeneous multiprocessor configurations; instruction sets; networking oriented data-driven processor; packet formats; parallelism; pipeline resources; real-time media processing; real-time protocol processing; sequential processing scheme; user requirements; Cities and towns; Fluctuations; Instruction sets; Nonhomogeneous media; Parallel processing; Pipelines; Protocols; Runtime; Telephony; Video compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Innovative Architecture for Future Generation High-Performance Processors and Systems, 2002. International Workshop on
  • ISSN
    1537-3223
  • Print_ISBN
    0-7695-1635-1
  • Type

    conf

  • DOI
    10.1109/IWIA.2002.1035024
  • Filename
    1035024