DocumentCode
2285793
Title
Low-voltage CMOS device scaling
Author
Chenming Hu
Author_Institution
California Univ., Berkeley, CA, USA
fYear
1994
fDate
16-18 Feb. 1994
Firstpage
86
Lastpage
87
Abstract
Discussions of device scaling are often based on simplistic device models. Much more accurate models have become available recently but remain largely unknown to the circuit and design community. This paper highlights some of these models by projecting low-voltage CMOS device trends.<>
Keywords
insulated gate field effect transistors; semiconductor device models; circuit design; device models; low-voltage CMOS device scaling; Capacitance; Clocks; Delay; Equations; Inverters; MOSFET circuits; SPICE; Semiconductor device modeling; Silicon on insulator technology; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-1844-7
Type
conf
DOI
10.1109/ISSCC.1994.344716
Filename
344716
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