An 80 k-transistor configurable 25 MPixels/s video compression processor unit

Author

Molloy, S. ; Schoner, B. ; Madisetti, A. ; Jain, R.

Author_Institution

Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

78

Lastpage

79

Abstract

To address the varied requirements of portable video applications, new processor units are required that can execute a variety of intraframe coding algorithms in real-time. Furthermore, low complexity is required, as the intraframe coder is only one element of the complete video compression system. Neither programmable video signal processors (VSPs) nor dedicated ASICs can satisfy all of the above needs. The video compression processor unit (VCPU) described in this paper is based on a configurable architecture. An efficiency comparison is presented between this processor unit, a programmable VSP E33 and three dedicated video ASICs.<>

Keywords

codecs; data compression; image coding; video equipment; video signals; 80 k-transistor; configurable architecture; intraframe coding algorithms; portable video; real-time; video compression processor unit; Application specific integrated circuits; CMOS technology; Clocks; Discrete cosine transforms; Finite impulse response filter; Image coding; Packaging; Power dissipation; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344719

Filename

344719