A single-chip MPEG2 video decoder LSI

Author

Demura, T. ; Oto, T. ; Kitagaki, K. ; Ishiwata, S. ; Otomo, G. ; Michinaka, S. ; Suzuki, S. ; Goto, N. ; Matsui, M. ; Hara, H. ; Nagamatsu, T. ; Seta, K. ; Shimazawa, T. ; Maeguchi, K. ; Odaka, T. ; Uetani, Y. ; Oku, T. ; Yamakage, T. ; Sakurai, T.

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

72

Lastpage

73

Abstract

This MPEG2 video decoder LSI decodes MPEG2 standard bit streams. The compression algorithm in the MPEG2 is based on discrete cosine transform (DCT), variable length coding, and motion compensation similar to the MPEG1, the earlier standard. However, the processing speed should be more than four times faster than MPEG1. Moreover, several algorithms and structures to handle interlaced pictures are added to the MPEG1 standard. This LSI decodes in real time all motion-compensation modes and picture structures in MPEG2 bit streams of not only CCIR601 but also HDTV resolution.<>

Keywords

CMOS integrated circuits; data compression; decoding; digital signal processing chips; discrete cosine transforms; large scale integration; motion estimation; reduced instruction set computing; video equipment; video signals; CCIR601; DCT; HDTV resolution; MPEG2 standard bit streams; MPEG2 video decoder LSI; compression algorithm; discrete cosine transform; interlaced pictures; motion compensation; motion-compensation modes; onchip RISC; real time decoding; single-chip decoder; variable length coding; Buffer storage; Decoding; Discrete cosine transforms; Displays; Image reconstruction; Large scale integration; Reduced instruction set computing; Streaming media; Transform coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344721

Filename

344721