Online DES control behavior verification via virtual supervisor

Vast majority of manufacturing devices and systems are controlled by programmable software logic controllers. The primary issues in design, development, and operation of such systems are related to the relative complexity of involved control logic. The focus for DES in supervisory control is how to deal to with uncontrollable events, blocking in the controlled system and unobservable events. This paper presents a new methodology for mapping operational pattern of States-Events-Times during control logic execution. This approach enables identification of conflicts, such as blockings or bottlenecks, which may occur due to exceptions (such as sensor failures). Proposed approach, relying on the historical data, pre-determined operational pattern, and relations of states-events-times, generates a virtual supervisor which not only enables return of the process to deterministic behavior, but also run-time verification of its properties. This new approach offers the flexibility to perform engineering changes, add new specifications, and facilitates future system modifications.