DocumentCode
2285904
Title
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
Author
Ogras, Umit Y. ; Marculescu, Radu ; Lee, Hyung Gyu ; Chang, Naehyuck
Author_Institution
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA
Volume
1
fYear
2006
fDate
6-10 March 2006
Abstract
Network-on-chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures have become very popular recently. However, they have poor topological properties such as long inter-node distances. In this paper, we address this very issue and explore the potential of partial NoC customization to improve both static and dynamic properties of the network significantly, while minimally affecting its regularity. Precise energy measurements on an FPGA prototype show that the improvement in network properties is achieved without a significant penalty in area and communication energy consumption
Keywords
circuit optimisation; field programmable gate arrays; integrated circuit design; logic design; network-on-chip; FPGA prototype; communication architecture optimization; dynamic properties; inter-node distances; mesh-like NoC architectures; network properties; networks-on-chip; partial NoC customization; shortest path; static properties; topological properties; Bandwidth; Intelligent networks; Mesh networks; Network topology; Network-on-a-chip; Repeaters; Routing; System recovery; Telecommunication traffic; Tiles;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 2006. DATE '06. Proceedings
Conference_Location
Munich
Print_ISBN
3-9810801-1-4
Type
conf
DOI
10.1109/DATE.2006.244068
Filename
1656980
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