A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 codec

Author

Toyokura, M. ; Saishi, M. ; Kurohmaru, S. ; Yamauchi, K. ; Imanishi, H. ; Ougi, T. ; Watabe, A. ; Matsumoto, Y. ; Morishige, T. ; Kodama, H. ; Miyagoshi, E. ; Okamoto, K. ; Gion, M. ; Minemaru, T. ; Ohtani, A. ; Araki, T. ; Aono, K. ; Takeno, H. ; Akiyama

Author_Institution

Matsushita Electr. Co. Ltd., Osaka, Japan

fYear

1994

fDate

16-18 Feb. 1994

Firstpage

74

Lastpage

75

Abstract

VDSP2 is a DSP for the MPEG2 algorithm which employs 0.5 /spl mu/m triple-layer-metal CMOS technology. By using this DSP, a real-time encoder and decoder specified in MPEG2 have been realized with two VDSP2s and a ME unit, and a VDSP2, respectively, at 80 MHz clock rate.<>

Keywords

CMOS integrated circuits; codecs; data compression; decoding; digital signal processing chips; image coding; pipeline processing; real-time systems; video equipment; video signals; 0.5 micron; 80 MHz; MPEG2 algorithm; MPEG2 codec; SIMD type vector-pipeline architecture; VDSP2; macroblock-level-pipeline; real-time decoder; real-time encoder; triple-layer-metal CMOS technology; video DSP; CMOS technology; Circuits; Codecs; Decoding; Digital signal processing; Discrete cosine transforms; Pipelines; Random access memory; Read-write memory; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1994. Digest of Technical Papers. 41st ISSCC., 1994 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-1844-7

Type

conf

DOI

10.1109/ISSCC.1994.344733

Filename

344733