DocumentCode :
228651
Title :
Design optimization of segmented-channel MOSFET using high-K dielectric material
Author :
Sujith, M.B. ; Nesamani, I. Flavia Princess ; Prabha, V. Lakshmi ; Chacko, Anoob Eapen ; Divakaran, Rekha
Author_Institution :
Electron. & Commun. Dept., Karunya Univ., Coimbatore, India
fYear :
2014
fDate :
13-14 Feb. 2014
Firstpage :
1
Lastpage :
5
Abstract :
Conventional MOSFET designs face many challenges as they are scaled down. The increased short channel effects in conventional MOSFET device paves the way for many device architectures. One such is the segmented-channel MOSFET (SegFET) structure, a more evolutionary solution for continued bulk MOSFET scaling. SegFETs are fabricated using a conventional process. The channel of the device is segmented. The areas between the channel stripes are filled with high-K material (Hafnia). This device also provides a higher performance, reduced short channel effects and reduced power consumption.
Keywords :
MOSFET; high-k dielectric thin films; low-power electronics; Hafnia high-K material; SegFET structure; continued bulk MOSFET scaling; design optimization; high-K dielectric material; power consumption reduction; segmented channel MOSFET; short channel effect reduction; Epitaxial growth; High K dielectric materials; Logic gates; MOSFET; Performance evaluation; Silicon; Substrates; SegFET; Shallow Trench Isolation; Very Shallow Trench Isolation; corrugated substrate;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics and Communication Systems (ICECS), 2014 International Conference on
Conference_Location :
Coimbatore
Print_ISBN :
978-1-4799-2321-2
Type :
conf
DOI :
10.1109/ECS.2014.6892718
Filename :
6892718
Link To Document :
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