Title :
Assessment of a MOSFET circuit model as a tool for device design down to 0.05 /spl mu/m
Author :
Biesemans, S. ; De Meyer, K.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
This report investigates in what respect the so called ´physical´ circuit model is a helpful tool to a device engineer. Gate, channel and source/drain (S/D) engineering are the three main themes for optimising the device characteristics. Whether a circuit model can provide quantitative information about the device geometric parameters is looked for. It is found that the basic I/sub ds/ model can be scaled down to 50 nm channel lengths covering most of the device design aspects.
Keywords :
MOSFET; semiconductor device models; 0.05 micron; MOSFET circuit model; device design; drain current model; short channel effect; Application specific processors; Degradation; Design engineering; Electronics industry; Equations; Intrusion detection; MOSFET circuits; Solid modeling; Substrates; Transconductance;
Conference_Titel :
Simulation of Semiconductor Processes and Devices, 1997. SISPAD '97., 1997 International Conference on
Conference_Location :
Cambridge, MA, USA
Print_ISBN :
0-7803-3775-1
DOI :
10.1109/SISPAD.1997.621398
