Design of a 32nm independent gate FinFET based SRAM cell with improved noise margin for low power application

In this paper Read Noise Margin (RNM), Write Noise margin (WNM) and standby power consumption of two, 6 transistor (6-T) FinFET based SRAM cell is presented. The write ability and RNM has been improved using pass transistor´s and pull up transistor´s back gate voltage without area penalty. For improving the performance, a separate word line WWL is used. Further, the effect of process variation on the SRAM cell performance due to variation in FinFET´s widths, lengths, threshold voltage (V_th) and gate oxide thickness (T_ox) was analyzed by Monte Carlo simulation. The simulation was carried out for 1000 values, assuming 3σ equal to 10 percent of the mean value. The whole work was accomplished using PTM (Predictive Technology Model) for 32nm FinFET by HSPICE simulation.