Title :
Systolic array for binary multiplier
Author :
Wang, L. ; Hartimo, I.
Author_Institution :
Helsinki Univ. of Technol., Espoo, Finland
Abstract :
A new systolic implementation is proposed for multiplication of two n-bit binary numbers. It greatly saves the array size compared to previous solutions, while the throughput is only slightly decreased. Therefore it is very suitable for VLSI array processors. The entire structure is connected in a pipeline
Keywords :
VLSI; digital signal processing chips; multiplying circuits; parallel algorithms; pipeline processing; systolic arrays; VLSI; array size; binary multiplier; n-bit binary numbers; parallel algorithms; pipeline connection; systolic array; throughput; Digital signal processing; Hardware; Parallel algorithms; Pipeline processing; Systolic arrays; Throughput; Very large scale integration;
Conference_Titel :
Speech, Image Processing and Neural Networks, 1994. Proceedings, ISSIPNN '94., 1994 International Symposium on
Print_ISBN :
0-7803-1865-X
DOI :
10.1109/SIPNN.1994.344804
