A model for a universally testable logic element

Author

Razavi, Hassan M. ; Elahi, Ata

Author_Institution

Dept. of Comput. Sci., North Carolina Univ., Charlotte, NC, USA

fYear

1995

fDate

26-29 Mar 1995

Firstpage

85

Lastpage

91

Abstract

A model is presented for a logic element to be used in the design of testable logic circuits. The logic element consists of a threshold gate and an exclusive-or. A circuit designed exclusively with such an element, according to the rules set here, can be tested for all data stuck-at faults. Only two predetermined test vectors are needed for testing any combinational circuit and four for any sequential circuit, for data stuck-at faults, regardless of the complexity of the circuit. A possible CMOS circuit realization for the model is given

Keywords

CMOS logic circuits; combinational circuits; logic gates; logic testing; sequential circuits; threshold logic; CMOS circuit; combinational circuit; data stuck-at faults; design; model; or gate; sequential circuit; test vectors; threshold gate; universally testable logic element; Circuit faults; Circuit testing; Computer science; Electronic mail; Integrated circuit modeling; Logic circuits; Logic testing; Sequential analysis; Turing machines; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Southeastcon '95. Visualize the Future., Proceedings., IEEE

Conference_Location

Raleigh, NC

Print_ISBN

0-7803-2642-3

Type

conf

DOI

10.1109/SECON.1995.513062

Filename

513062