Real-time MPEG-2 software decoding with a dual-issue RISC processor

A single chip system for real-time MPEG-2 decoding can be created by integrating a dual-issue RISC processor with a small dedicated hardware for the variable length decoding (VLD) and block loading processes; a 32 KB instruction RAM; and a 16 KB data RAM. The VLD hardware performs the Huffman decoding on the input data. The block loader performs the half-sample prediction for motion compensation and acts as a direct memory access controller for the RISC processor. The dual-issue RISC processor, running at 250 MHz, is enhanced with a set of key sub-word and multimedia instructions for a sustained peak performance of 1000 MOPS. With this setup for MPEG-2 decoding applications, bi-directionally predicted non-intra blocks are decoded in less than 800 cycles, leading to a single chip, real-time MPEG-2 decoding system