• DocumentCode
    228692
  • Title

    Comparison of serial data-input CRC and parallel data-input CRC design for CRC-8 ATM HEC employing MLFSR

  • Author

    Panda, Avipsa S. ; Kumar, G.L.

  • Author_Institution
    Sch. of Electron., KIIT Univ., Bhubaneswar, India
  • fYear
    2014
  • fDate
    13-14 Feb. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Cyclic Redundancy check (CRC) is primarily used in the physical layer of transmission protocols (viz., Ethernet and Bluetooth). CRC computation can be done in two ways; either serial computation or parallel computation. CRC computation implement linear feedback shift registers (LFSRs). The proposed paper gives an insight of serial and parallel implementation of CRC 8- CCITT widely used in Header Error Control in Asynchronous Transfer Mode (ATM HEC).
  • Keywords
    asynchronous transfer mode; cyclic redundancy check codes; parallel architectures; shift registers; CRC 8 ATM HEC; MLFSR; asynchronous transfer mode; cyclic redundancy check; header error control; linear feedback shift registers; parallel computation; parallel data input CRC; physical layer; serial computation; serial data input CRC; transmission protocols; Timing; CRC; LFSR; MLFSR; parallel architecture of CRC; serial architecture of CRC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics and Communication Systems (ICECS), 2014 International Conference on
  • Conference_Location
    Coimbatore
  • Print_ISBN
    978-1-4799-2321-2
  • Type

    conf

  • DOI
    10.1109/ECS.2014.6892739
  • Filename
    6892739
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=228692