DocumentCode :
2287150
Title :
Implementing grayscale morphological operators with a compact ranked order extractor circuit
Author :
Poikonen, Jonne ; Paasio, Afu
Author_Institution :
Dept. of Inf. Technol., Turku Univ., Finland
fYear :
2002
fDate :
22-24 Jul 2002
Firstpage :
646
Lastpage :
653
Abstract :
Mathematical morphology provides tools for many image processing tasks. In this paper we discuss the implementation of grayscale morphological operators of erosion, dilation and reconstruction with a hardware efficient ranked order filter circuit. By using dedicated hardware for these basic operations a higher performance of processing more complex functions in a massively parallel processor array can be achieved. Because the circuit realization of the ranked order filter used is very compact, the area required for one processing cell can be kept low. Simulations of the operation were performed with a 0.18 μm digital CMOS technology.
Keywords :
CMOS digital integrated circuits; cellular neural nets; image reconstruction; mathematical morphology; neural chips; cellular neural network; digital CMOS technology; grayscale morphological operators; hardware efficient ranked order filter circuit; image processing tasks; massively parallel processor array; mathematical morphology; ranked order filter; Cellular neural networks; Circuits; Data mining; Filters; Gray-scale; Hardware; Image processing; Image reconstruction; Morphological operations; Morphology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Cellular Neural Networks and Their Applications, 2002. (CNNA 2002). Proceedings of the 2002 7th IEEE International Workshop on
Print_ISBN :
981-238-121-X
Type :
conf
DOI :
10.1109/CNNA.2002.1035107
Filename :
1035107
Link To Document :
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