An efficient pipelined VLSI implementation of rank order filter

An efficient pipelined VLSI implementation of rank order filter based on the ordering property is proposed. In the previous works, this filter required many iterations in the bit-serial implementation of the positive Boolean function (PBF) and used a large number of counters, comparators and many AND-OR logic array inputs in a parallel architecture to output an M-th order sample. This limited the real-time applications for large window size. Based on the ordering property of the values of the elements in the m-array, we proposed a pipeline architecture to fold the parallel data flow in order to reduce the hardware complexity without loss of performance. The proposed design can also realize the concurrent search method for the PBF to output an M-th order sample. Compared with previous works, the hardware complexity is reduced from O(2^r) to O(2^r/2) area-time complexity and the latency approaches that of a parallel implementation