A new method of evolving hardware design based on IIC bus and AT24C02

Author

Li, Kangshun ; Chen, Yan ; Liu, Hezuan

Author_Institution

Sch. of Inf., South China Agric. Univ., Guangzhou, China

fYear

2012

fDate

6-8 July 2012

Firstpage

104

Lastpage

107

Abstract

A new method of evolving hardware design based on I2C bus and AT24C02 is presented in this paper. This method has expanded the application of I2C-bus, it is implemented on A FPGA/ SOPC by using I2C-bus and T24C02 to simulated I2C-bus transmission timing, it change the method of evolving hardware design by using I2C-bus and AT24C02 but not using evolutionary algorithm, overcome the disadvantage of long time of the traditional method, and achieve a fast, high efficiency and higher accuracy I2C interface design techniques. The experiments show that the circuits evolved by using this new method based on I2C-bus andAT24C02 communication interface can save transmission time, increase the bus utilization, and has achieved good results.

Keywords

field programmable gate arrays; system buses; AT24C02 communication interface; FPGA; I2C bus transmission timing; I2C interface design; IIC bus; SOPC; bus utilization; evolutionary algorithm; evolving hardware design; Clocks; Digital signal processing; Educational institutions; Field programmable gate arrays; Hardware; Timing; AT24C02; FPGA/SOPC; I2C bus; Nios II;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Control and Automation (WCICA), 2012 10th World Congress on

Conference_Location

Beijing

Print_ISBN

978-1-4673-1397-1

Type

conf

DOI

10.1109/WCICA.2012.6357848

Filename

6357848