DocumentCode :
2287517
Title :
A novel approach to design a massively parallel application specific architecture for image recognition systems
Author :
Farroha, B.S. ; Deshmukh, R.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Florida Inst. of Technol., Melbourne, FL, USA
fYear :
1995
fDate :
26-29 Mar 1995
Firstpage :
293
Lastpage :
299
Abstract :
The goal of the paper is to present a novel approach for designing massively parallel architectures for image recognition systems. Massive parallel hardware produces high speed image recognition. Hardware architectures work much faster and are more effective for application specific processing than a software-based image recognition system. The concept of designing optimal image recognition systems with high speed, low complexity, good portability, and low cost has been present for a long time. The authors have considered the basic design factors, simple and regular design, concurrency and communication, and balancing computation with I/O. The technique presented provides a new method of designing an image recognition system by concentrating on modularity and massive parallelism. This is accomplished through the design of a processing element layer, local communicator layer, and network of new image layer. The processing element (PE) layer performs the basic recognition functions on individual pixels through logical operations. Both the local communicator and network of new image layers institute a mesh network topology, which has proven to be the fastest and most efficient. The local communicator layer has the most important function, it communicates with the other two layers, combines results from the PE layer, and houses the main control unit. All layers work simultaneously, or in other words, in a parallel fashion. The flow diagram of a CAD designer algorithm, based on this new design technique, is presented
Keywords :
CAD; VLSI; application specific integrated circuits; digital signal processing chips; image recognition; parallel architectures; CAD designer algorithm; communication; concurrency; design factors; image recognition systems; local communicator layer; logical operations; main control unit; massive parallelism; massively parallel application specific architecture; mesh network topology; modularity; network of new image layer; processing element layer; Algorithm design and analysis; Application software; Concurrent computing; Cost function; Design methodology; Hardware; Image recognition; Parallel architectures; Parallel processing; Process design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Southeastcon '95. Visualize the Future., Proceedings., IEEE
Conference_Location :
Raleigh, NC
Print_ISBN :
0-7803-2642-3
Type :
conf
DOI :
10.1109/SECON.1995.513105
Filename :
513105
Link To Document :
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