An embedded decryption/decompression engine using Handel-C

Speed and security of data streams are two key factors in different areas such as data communication and multimedia. Compression algorithms are applied to data streams to increase their communication speed while encryption algorithms are used for assuring the security of the data transfer. AES and LZ77 are two well known algorithms for data encryption and compression respectively. In this paper we propose a model to implement both algorithms, decryption and decompression, in a field programmable gate array chip. Such a design must address the issues of optimal resource usage of the FPGA, and balance between the throughput of both algorithms. Handel-C is considered as the specification language for this design.