Title :
Model-based architectural design and verification of scalable embedded DSP systems-a RASSP approach
Author :
Dung, L.-R. ; Madisetti, V.K. ; Hines, J.W.
Author_Institution :
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fDate :
30 Oct-1 Nov 1996
Abstract :
The paper describes how rapid model-year architectural synthesis (e.g., HW/SW codesign) of embedded signal processors can be performed to optimize various cost objective functions using a reuse library of model, followed by simulation based optimization. Sponsored as part of DARPA´s RASSP program, this approach has developed and released a number of interoperable and verified architectural component libraries at the system level (processors, communication protocols, and topologies). While these libraries have been used in actual demonstrations of avionics and military systems, such as the MIT Lincoln Laboratory´s SAR Benchmark, the F-14 legacy Infrared Search and Track System (IRST), and as part of NASA/JPL´s Remote Exploration/Experimentation (REE) program studies, the authors introduce the methodology of conceptual prototyping and establish the requirements and features of the proposed environment. They also illustrate its use on some common applications with relatively sophisticated architectural building blocks, such as IEEE SCI protocol and Analog Devices´ SHARC processor family
Keywords :
digital signal processing chips; formal specification; formal verification; optimisation; protocols; real-time systems; reconfigurable architectures; signal processing; software libraries; software prototyping; virtual machines; Analog Devices SHARC processor family; IEEE SCI protocol; RASSP approach; conceptual prototyping; embedded signal processors; interoperable architectural component libraries; model-based architectural design; optimized cost objective functions; requirements; reuse library; scalable embedded DSP systems; simulation based optimization; verification; verified architectural component libraries; Aerospace electronics; Cost function; Digital signal processing; Process design; Prototypes; Signal processing; Signal synthesis; Software libraries; Software prototyping; Topology;
Conference_Titel :
VLSI Signal Processing, IX, 1996., [Workshop on]
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-3134-6
DOI :
10.1109/VLSISP.1996.558314